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Curricular information is subject to change
1. Learn about basic building blocks of all-digital phase-locked loop (ADPLL)
2. Learn to behaviorally simulate the ADPLL
3. Learn about the digitally controlled power amplifier
4. Learn about digitally intensive discrete-time receiver (DT-RX)
5. Understand the tradeoff of system requirements on circuits specifications
6. Become conversant with the relevant latest literature
Student Effort Type | Hours |
---|---|
Lectures | 24 |
Specified Learning Activities | 36 |
Autonomous Student Learning | 48 |
Total | 108 |
Basic signal processing; basic knowledge of Matlab.
Description | % of Final Grade | Timing |
---|---|---|
Examination: Final exam | 40 |
2 hour End of Trimester Exam |
Assignment: Homework assignments | 40 |
Throughout the Trimester |
Essay: IEEE JSSC journal reading | 20 |
Week 12 |
Compensation
This module is not passable by compensation
Resit Opportunities
In-semester assessment
Remediation
If you fail this module you may repeat, resit or substitute where permissible.
Name | Role |
---|---|
Dr Teerachot Siriburanon | Lecturer / Co-Lecturer |