EEEN40610 Digital RF

Academic Year 2017/2018

The past decade has successfully brought all-digital techniques to radio frequency (RF) synthesizers and transmitters, as well as digitally intensive techniques to receivers. In addition, digital assistance is applied to RF circuits to improve performance and power consumption. This module will introduce basic concepts of the digital RF approach and walk through the major building blocks that comprise the new RF transceiver architecture:
1. All-digital phase-locked loop (ADPLL) comprising: digitally-controlled oscillator (DCO), time-to-digital converter (TDC), and digital loop filter.
2. All-digital transmitter featuring ADPLL with wideband modulation capability, and comprising digitally-controlled power amplifier (DPA)
3. Direct-sampling discrete-time receiver comprising switched-cap circuits that perform various FIR and IIR filter operations.
Homework exercises use Matlab to model and simulate the above three subsystems.

1. Introduction to the topics of digital RF and digitally-assisted RF
2. Digitally-controlled oscillator (DCO), its phase noise modeling and simulation
3. DCO interface: sigma-delta modulation, dynamic element matching, DCO gain normalization
4. Principles of phase-domain frequency synthesis: all-digital PLL (ADPLL)
5. Time-to-digital converter (TDC) and metastability
6. ADPLL closed-loop behavior
7. Direct frequency modulation of ADPLL
8. Principles of switched-mode and digital power amplifier (DPA)
9. DPA modeling and non-linearities; predistortion
10. Principles of a discrete-time (DT) receiver
11. Signal processing of a DT mixer: IIR, FIR and decimation
12. DT receiver modeling and simulation
13. Special topics, project presentations, etc.

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Curricular information is subject to change

Learning Outcomes:

1. Learn about basic building blocks of all-digital phase-locked loop (ADPLL)
2. Learn to behaviorally simulate the ADPLL
3. Learn about the digitally controlled power amplifier
4. Learn about digitally intensive discrete-time receiver (DT-RX)
5. Understand the tradeoff of system requirements on circuits specifications
6. Become conversant with the relevant latest literature

Student Effort Hours: 
Student Effort Type Hours
Specified Learning Activities


Autonomous Student Learning






Requirements, Exclusions and Recommendations
Learning Requirements:

Basic signal processing; basic knowledge of Matlab.

Description % of Final Grade Timing
Assignment: Homework assignments


Throughout the Trimester
Examination: Final exam


2 hour End of Trimester Exam
Essay: IEEE JSSC journal reading


Week 12


This module is not passable by compensation

Resit Opportunities

In-semester assessment


If you fail this module you may repeat, resit or substitute where permissible.

Name Role
Dr Teerachot Siriburanon Lecturer / Co-Lecturer