Learning Outcomes:
Gain skills in designing ADC and DAC circuits.Refine mixed-signal circuit design and behavioral modeling experience in Cadence CAD tools. Understand mixed-signal circuit tradeoffs on system performance.
Curricular information is subject to change.
Gain skills in designing ADC and DAC circuits.Refine mixed-signal circuit design and behavioral modeling experience in Cadence CAD tools. Understand mixed-signal circuit tradeoffs on system performance.
Student Effort Type | Hours |
---|---|
Specified Learning Activities | 36 |
Autonomous Student Learning | 24 |
Lectures | 24 |
Computer Aided Lab | 24 |
Total | 108 |
Not applicable to this module.
Description | Timing | Component Scale | % of Final Grade | ||
---|---|---|---|---|---|
Assignment(Including Essay): Homework assignments and reports on laboratory work. Timing may vary. | Week 3, Week 4, Week 5, Week 6, Week 7, Week 8, Week 9, Week 10, Week 11 | Standard conversion grade scale 40% | No | 40 |
No |
Assignment(Including Essay): IEEE journal paper reading. | Week 12 | Standard conversion grade scale 40% | No | 20 |
No |
Exam (In-person): Written exam at end of trimester | End of trimester Duration: 2 hr(s) |
Standard conversion grade scale 40% | No | 40 |
No |
Resit In | Terminal Exam |
---|---|
Autumn | Yes - 2 Hour |
• Feedback individually to students, post-assessment
Not yet recorded.
Name | Role |
---|---|
Dr Minh Hieu Nguyen | Lecturer / Co-Lecturer |
Dr Viet Nguyen | Lecturer / Co-Lecturer |
Dr Teerachot Siriburanon | Lecturer / Co-Lecturer |
Spring | Lecture | Offering 1 | Week(s) - 20, 21, 22, 23, 24, 25, 26, 29, 30, 31, 32, 33 | Thurs 12:00 - 12:50 |
Spring | Laboratory | Offering 1 | Week(s) - 21, 22, 23, 24, 25, 26, 29, 30, 31, 32, 33 | Thurs 13:00 - 14:50 |
Spring | Lecture | Offering 1 | Week(s) - 20, 21, 22, 23, 24, 25, 26, 29, 30, 31, 32, 33 | Tues 14:00 - 14:50 |