Learning Outcomes:
Gain skills in designing ADC and DAC circuits.Refine mixed-signal circuit design and behavioral modeling experience in Cadence CAD tools. Understand mixed-signal circuit tradeoffs on system performance.
Curricular information is subject to change.
Gain skills in designing ADC and DAC circuits.Refine mixed-signal circuit design and behavioral modeling experience in Cadence CAD tools. Understand mixed-signal circuit tradeoffs on system performance.
Student Effort Type | Hours |
---|---|
Lectures | 24 |
Computer Aided Lab | 24 |
Specified Learning Activities | 36 |
Autonomous Student Learning | 24 |
Total | 108 |
Not applicable to this module.
Description | Timing | Component Scale | % of Final Grade | |||
---|---|---|---|---|---|---|
Assignment: Homework assignments and lab reports | Throughout the Trimester | n/a | Standard conversion grade scale 40% | No | 40 |
No |
Essay: IEEE journal paper reading | Week 12 | n/a | Standard conversion grade scale 40% | No | 20 |
No |
Examination: Final exam | 2 hour End of Trimester Exam | No | Standard conversion grade scale 40% | No | 40 |
No |
Resit In | Terminal Exam |
---|---|
Autumn | Yes - 2 Hour |
• Feedback individually to students, post-assessment
Not yet recorded.
Name | Role |
---|---|
Dr Minh Hieu Nguyen | Lecturer / Co-Lecturer |
Dr Viet Nguyen | Lecturer / Co-Lecturer |
Dr Teerachot Siriburanon | Lecturer / Co-Lecturer |