Learning Outcomes:
Gain skills to design core analog circuits in CMOS integrated circuits.
Gain analogue design experience in Cadence CAD tools.
Analogue Integrated Circuits (EEEN40570)
Curricular information is subject to change.
Analysis and simulation of elementary transistor stages, current mirrors, operational amplifiers, supply- and temperature-independent bias, and reference circuits. Overview of integrated circuit technologies, circuit components, component variations and practical design paradigms. Differential circuits, frequency response, and feedback will also be covered. Performance evaluation using computer-aided design tools.
WARNING: This is a Masters' level module and a lot of independent work will be expected!
WARNING: This is a Masters' level module and a lot of independent work will be expected!
About this Module
Student Effort Hours:
| Student Effort Type | Hours |
|---|---|
| Specified Learning Activities | 36 |
| Autonomous Student Learning | 24 |
| Lectures | 24 |
| Computer Aided Lab | 24 |
| Total | 108 |
Approaches to Teaching and Learning:
Traditional approach.Requirements, Exclusions and Recommendations
Learning Requirements:Basic signals & systems, circuit theory and analog electronic circuits.
Module Requisites and Incompatibles
Not applicable to this module.Assessment Strategy
| Description | Timing | Component Scale | % of Final Grade | ||
|---|---|---|---|---|---|
| Assignment(Including Essay): Homework assignments and reports on laboratory work. Timing may vary. | Week 3, Week 4, Week 5, Week 6, Week 7, Week 8, Week 9, Week 10, Week 11 | Standard conversion grade scale 40% | No | 40 |
No |
| Exam (In-person): Written exam at end of trimester. | End of trimester Duration: 2 hr(s) |
Standard conversion grade scale 40% | No | 40 |
No |
| Individual Project: Final circuit design project | Week 12 | Standard conversion grade scale 40% | No | 20 |
No |
| Resit In | Terminal Exam |
|---|---|
| Spring | Yes - 2 Hour |
Feedback Strategy/Strategies
• Feedback individually to students, post-assessment
How will my Feedback be Delivered?
Not yet recorded.
| Name | Role |
|---|---|
| Dr Minh Hieu Nguyen | Lecturer / Co-Lecturer |
| Dr Viet Nguyen | Lecturer / Co-Lecturer |
| Dr Teerachot Siriburanon | Lecturer / Co-Lecturer |
Timetabling information is displayed only for guidance purposes, relates to the current Academic Year only and is subject to change.
| Autumn | Lecture | Offering 1 | Week(s) - Autumn: All Weeks | Tues 15:00 - 15:50 |
| Autumn | Lecture | Offering 1 | Week(s) - Autumn: All Weeks | Wed 12:00 - 12:50 |
| Autumn | Practical | Offering 1 | Week(s) - Autumn: All Weeks | Thurs 12:00 - 13:50 |
| Autumn | Practical | Offering 2 | Week(s) - Autumn: All Weeks | Wed 15:00 - 16:50 |