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Curricular information is subject to change
Gain skills to design core analog circuits in CMOS integrated circuits.
Gain analogue design experience in Cadence CAD tools.
Student Effort Type | Hours |
---|---|
Lectures | 24 |
Computer Aided Lab | 24 |
Specified Learning Activities | 36 |
Autonomous Student Learning | 24 |
Total | 108 |
Basic signals & systems, circuit theory and analog electronic circuits.
Description | Timing | Component Scale | % of Final Grade | ||
---|---|---|---|---|---|
Examination: Final exam | 2 hour End of Trimester Exam | No | Standard conversion grade scale 40% | No | 40 |
Project: Final circuit design project | Week 12 | n/a | Standard conversion grade scale 40% | No | 20 |
Assignment: Homework assignments, lab reports | Throughout the Trimester | n/a | Standard conversion grade scale 40% | No | 40 |
Resit In | Terminal Exam |
---|---|
Spring | Yes - 2 Hour |
• Feedback individually to students, post-assessment
Not yet recorded.
Name | Role |
---|---|
Dr Minh Hieu Nguyen | Lecturer / Co-Lecturer |
Dr Viet Nguyen | Lecturer / Co-Lecturer |
Dr Teerachot Siriburanon | Lecturer / Co-Lecturer |
Lecture | Offering 1 | Week(s) - Autumn: All Weeks | Tues 15:00 - 15:50 |
Lecture | Offering 1 | Week(s) - Autumn: All Weeks | Wed 12:00 - 12:50 |
Practical | Offering 1 | Week(s) - Autumn: All Weeks | Thurs 13:00 - 14:50 |
Practical | Offering 2 | Week(s) - Autumn: All Weeks | Fri 15:00 - 16:50 |