Learning Outcomes:
Gain skills to design core analog circuits in CMOS integrated circuits.
Gain analogue design experience in Cadence CAD tools.
Curricular information is subject to change.
Gain skills to design core analog circuits in CMOS integrated circuits.
Gain analogue design experience in Cadence CAD tools.
Student Effort Type | Hours |
---|---|
Lectures | 24 |
Computer Aided Lab | 24 |
Specified Learning Activities | 36 |
Autonomous Student Learning | 24 |
Total | 108 |
Basic signals & systems, circuit theory and analog electronic circuits.
Description | Timing | Component Scale | % of Final Grade | |||
---|---|---|---|---|---|---|
Assignment: Homework assignments, lab reports | Throughout the Trimester | n/a | Standard conversion grade scale 40% | No | 40 |
No |
Examination: Final exam | 2 hour End of Trimester Exam | No | Standard conversion grade scale 40% | No | 40 |
No |
Project: Final circuit design project | Week 12 | n/a | Standard conversion grade scale 40% | No | 20 |
No |
Resit In | Terminal Exam |
---|---|
Spring | Yes - 2 Hour |
• Feedback individually to students, post-assessment
Not yet recorded.
Name | Role |
---|---|
Dr Teerachot Siriburanon | Lecturer / Co-Lecturer |