EEEN40280 Digital & Embedded Systems

Academic Year 2022/2023

This module deals with the design and implementation of embedded systems, involving a processor, software (or firmware) and other hardware. Topics include architectures and interfacing of typical processors, programming in C and assembly language to interact with hardware in real time, design and verification of systems involving a mix of hardware and software.

The module will have an emphasis on problem-based learning. Design assignments will require significant time during the trimester, and will involve working in a team and collaborating with others. Assessment of these assignments will be largely based on written reports, supplemented by interview where necessary.

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Curricular information is subject to change

Learning Outcomes:

On successful completion of this module, students should be able to:
1. Design a digital system involving an embedded processor and other hardware;
2. Write software for an embedded system;
3. Use appropriate software tools in the design and verification of such systems;
4. Work in a team and collaborate effectively with other members of the team;
5. Maintain proper documentation and communicate the results of their work.

Indicative Module Content:

1 - A brief introduction to embedded systems and to the module;
2 - Programming in assembly language, using an 8-bit microcontroller as an example;
3 - Microcontroller hardware, using the same 8-bit microcontroller as an example;
4 - Interfaces in embedded systems, including serial bus protocols;
5 - Programming in C for embedded systems (assuming knowledge of C programming);
6 - Processor bus structures, in general and using AMBA examples;
7 - Review of hardware design at register transfer level and hardware description language (assuming prior knowledge);
8 - Microcontroller hardware and instruction set, using ARM 32-bit microcontrollers as examples;
9 - A brief introduction to caches as used in embedded systems;
10 - A brief introduction to operating systems, with emphasis on embedded systems;
11 - Embedded system design.

Student Effort Hours: 
Student Effort Type Hours
Specified Learning Activities

12

Autonomous Student Learning

48

Lectures

24

Tutorial

4

Laboratories

33

Total

121

Approaches to Teaching and Learning:
This module uses a mix of lectures and problem-based learning. Some reasonably large design assignments will account for more than half of the total workload in this module - that will be a mix of hands-on work in the laboratory and design work that can be done elsewhere.

Lectures will be in person and attendance will be expected.
 
Requirements, Exclusions and Recommendations
Learning Requirements:

Digital system design at register transfer level is required. Knowledge of a hardware description language is also required. Verilog or SystemVerilog is preferred, but VHDL is acceptable. As an example, the module EEEN30190 Digital System Design provides the required prior knowledge.

Computer programming in C is required. As an example, the module EEEN20010 Computer Engineering provides the required prior knowledge.


Module Requisites and Incompatibles
Not applicable to this module.
 
Assessment Strategy  
Description Timing Open Book Exam Component Scale Must Pass Component % of Final Grade
Assignment: Design assignments during the trimester. Details of assignment weight and submission dates will be provided on Brightspace. Throughout the Trimester n/a Graded No

50

Examination: Written examination, invigilated, with access to lecture notes and one textbook. 2 hour End of Trimester Exam Yes Standard conversion grade scale 40% No

50


Carry forward of passed components
Yes
 
Resit In Terminal Exam
Summer No
Please see Student Jargon Buster for more information about remediation types and timing. 
Feedback Strategy/Strategies

• Feedback individually to students, post-assessment
• Group/class feedback, post-assessment

How will my Feedback be Delivered?

For assignments, students will receive written feedback on the report and code submitted. For the terminal exam, students may request to view their scripts.

Name Role
Dr Barry Cardiff Lecturer / Co-Lecturer
Timetabling information is displayed only for guidance purposes, relates to the current Academic Year only and is subject to change.
 
Spring
     
Lecture Offering 1 Week(s) - 20, 21, 23, 24, 25, 26, 29, 30, 32, 33 Mon 10:00 - 10:50
Lecture Offering 1 Week(s) - 20, 21, 22, 23, 24, 25, 26, 29, 30, 31, 32, 33 Thurs 13:00 - 13:50
Tutorial Offering 1 Week(s) - 20, 21 Tues 11:00 - 12:50
Laboratory Offering 1 Week(s) - 20, 21, 22, 23, 24, 25, 26, 29, 30, 31, 32, 33 Tues 14:00 - 16:50
Laboratory Offering 2 Week(s) - 20, 21, 22, 23, 24, 25, 26, 29, 30, 31, 32, 33 Wed 09:00 - 11:50
Spring