On successful completion of this module, students should be able to:
1. Analyse a digital system and predict its behaviour, timing, etc.;
2. Design a relatively complex digital system at register transfer level (RTL);
3. Describe an RTL diagram using the Verilog hardware description language;
4. Design a verification plan for a digital system, and create a testbench to implement that plan;
5. Use relevant software tools to simulate a digital system and to implement a digital system on FPGA;
6. Communicate the results of their work.

Design - How to take a description of how a system should behave, break it down into functional blocks that can implement that behaviour, and then design hardware to implement each of those blocks. There is no simple step-by-step procedure for this - it requires creative thinking as well as an understanding of the basic logic elements.

RTL diagrams - In most of this module, you will design digital systems down to register-transfer level (RTL), and capture those designs in RTL diagrams.

Hardware description language (HDL). You will use the Verilog HDL to describe your RTL diagrams in a way that can be interpreted by software tools, both for simulation and for synthesis (translation into a logic circuit).

Verification - Checking carefully that a design behaves as required is an important part of the design process. The first step is to design a verification plan - a sequence of tests that will prove that the design is good. Then the plan must be implemented in a testbench - in this module, also described in Verilog.

Timing - It is not enough that the design behaves as required, it must do it reliably, usually at high speed. Digital logic elements have time delays and timing constraints. Your design must satisfy these contraints...

Arithmetic - Digital hardware is often used to process numerical values, so you will learn how arithmetic operations are performed in hardware, and how to describe this in Verilog.

Implementation - Some of the issues involved in converting a design into hardware, either on FPGA (configurable logic), or as a CMOS integrated circuit.

Good understanding of combinational and sequential logic circuits, to the level of EEEN20050.

Familiarity with small digital systems such as counters and state machines.
Knowledge of binary arithmetic.

• Feedback individually to students, post-assessment
• Group/class feedback, post-assessment

For the design assignments, written feedback will be provided on the reports submitted. For a group report, this will be feedback to the group. For an individual report, this will be feedback to the student who submitted the report. For the terminal exam, students can request to view their script.