EEEN3012J Embedded Systems and Software

Academic Year 2021/2022

This module deals with the design and implementation of digital systems involving an embedded processor and software. Topics will include architectures and interfacing of typical processors, programming in C and assembly language to interact with hardware in real time, design and verification of systems involving a mix of hardware and software.

Show/hide contentOpenClose All

Curricular information is subject to change

Learning Outcomes:

design and implementation of digital systems
Architectures and interfacing of typical processors
programming in C and assembly language to interact with hardware in real time
design and verification of systems involving a mix of hardware and software.

Student Effort Hours: 
Student Effort Type Hours
Autonomous Student Learning

60

Lectures

24

Laboratories

24

Total

108

Approaches to Teaching and Learning:
Lectures where material is explained coupled with Labs where the students see first had the principles.
 
Requirements, Exclusions and Recommendations

Not applicable to this module.


Module Requisites and Incompatibles
Pre-requisite:
EEEN3002J - Microcontrollers

Required:
BDIC1034J - College English 1, BDIC1035J - College English 2, BDIC1036J - College English 3, BDIC1037J - College English 4, BDIC1047J - English for Uni Studies BDIC, BDIC1048J - English Gen Acad Purposes BDIC, BDIC2007J - English for Spec Acad Purposes, BDIC2015J - Acad Wrt & Comm Skills

Equivalents:
Embedded Systems (EEEN3007J)


 
Assessment Strategy  
Description Timing Open Book Exam Component Scale Must Pass Component % of Final Grade
Continuous Assessment: Labs/Assignments Throughout the Trimester n/a Standard conversion grade scale 40% No

50

Examination: Examination Throughout the Trimester No Standard conversion grade scale 40% No

50


Carry forward of passed components
Yes
 
Remediation Type Remediation Timing
In-Module Resit Prior to relevant Programme Exam Board
Please see Student Jargon Buster for more information about remediation types and timing. 
Feedback Strategy/Strategies

• Group/class feedback, post-assessment

How will my Feedback be Delivered?

Not yet recorded.

Name Role
Qingyuan Wang Tutor
Timetabling information is displayed only for guidance purposes, relates to the current Academic Year only and is subject to change.
 

There are no rows to display