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Curricular information is subject to change
design and implementation of digital systems
Architectures and interfacing of typical processors
programming in C and assembly language to interact with hardware in real time
design and verification of systems involving a mix of hardware and software.
Hardware design (verilog)
SoC design
Programming for the SoC developed.
Student Effort Type | Hours |
---|---|
Lectures | 30 |
Laboratories | 24 |
Autonomous Student Learning | 60 |
Total | 114 |
Not applicable to this module.
Description | Timing | Component Scale | % of Final Grade | ||
---|---|---|---|---|---|
Continuous Assessment: Labs/Assignments | Throughout the Trimester | n/a | Standard conversion grade scale 40% | No | 50 |
Examination: Examination | Throughout the Trimester | No | Standard conversion grade scale 40% | No | 50 |
Remediation Type | Remediation Timing |
---|---|
In-Module Resit | Prior to relevant Programme Exam Board |
• Group/class feedback, post-assessment
Not yet recorded.