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COMP30660

Academic Year 2025/2026

Computer Architecture & Organistion (Conversion) (COMP30660)

Subject:
Computer Science
College:
Science
School:
Computer Science
Level:
3 (Degree)
Credits:
5
Module Coordinator:
Professor Chris Bleakley
Trimester:
Spring
Mode of Delivery:
Blended
Internship Module:
No
How will I be graded?
Letter grades

Curricular information is subject to change.

This module explains how computers work. The module contains the following chapters:

1. Digital circuits. This chapter describes how electronic digital circuits work.
2. Combinational Logic Design. This chapter describes how useful digital circuits can be designed using logic gates.
3. Sequential Logic Design. This chapter describes how useful digital circuits with memory can be designed using logic gates.
4. Computer Architecture. This chapter describes how low-level software can be written for computers.
5. Digital Building Blocks. This chapter describes how commonly used digital circuit components can be built.
6. Microarchitecture. This chapter describes how a computer can be implemented using building blocks.
7. Memory Systems. This chapter describes how computer memory can be organised for increased performance.

The module focuses on the hardware/software interface of the open-source RISC-V processor.

About this Module

Learning Outcomes:

On completion of this module, students are expected to be able to:
Use number systems for calculations.
Explain the fundamentals of logic gates, digital electronics, transistors and integrated circuits.
Design combinatorial circuits.
Use Boolean algebra.
Use Karnaugh maps to design circuits.
Explain the implementation of latches and flip-flops.
Design finite state machines.
Perform calculations on circuit timing.
Explain the implementation of fundamental digital building blocks.
Write programs in assembly language.
Translate assembly instructions into machine instructions.
Explain the typical tool suite for developing software.
Explain the implementation of fundamental computer microarchitectures.
Assess the performance of computer microarchitectures.
Explain the implementation of fundamental computer memory systems.l
Assess the performance of computer memory systems.

Indicative Module Content:

The chapters will contain the following content:

1. Digital circuits covers number systems (including binary), Boolean logic gates, digital electronics, transistors and computer chips.
2. Combinational Logic Design covers Boolean equations, Boolean algebra, x’s and z’s, Karnaugh maps, simple building blocks and timing.
3. Sequential Logic Design covers latches and flip-flops, synchronous logic design, finite state machines and timing.
4. Computer Architecture covers assembly language, programming, machine language and software development tools.
5. Digital Building Blocks covers arithmetic circuits, numbers systems (revisited), counters and shift registers.
6. Microarchitecture covers a number of microarchitectures including single-clock, multiple cycle and pipelined.
7. Memory Systems covers memory performance, memory caches and virtual memory.

The approximate schedule is as follows:

The module closely follows the Harris and Harris textbook (see below).

Student Effort Hours:
Student Effort Type Hours
Lectures

24

Practical

16

Autonomous Student Learning

70

Total

110


Approaches to Teaching and Learning:
The module is delivered via a series of online video lectures, in-person lab sessions, in-person tests and an in-person end-of-semester examination.

The lectures for the module will be released as a series of online videos. A number of videos will be released every week.

There will be an in-person lab session every week. During the lab session, the students will be expected to complete a worksheet based on the lecture content. The worksheet will be designed around group work. The worksheets will focus on designing digital circuits and writing assembly code. The students’ worksheet solutions will not be graded. Sample worksheet solutions will be available.

There will be two in-person in-lab tests. The tests will be in pen-and-paper, closed-book format. Each test will be 1 hour 30 minutes in duration. The tests will be based on the content in the lectures and the worksheets. The tests will be graded.

At the end of the trimester, there will be a 2 hour in-person, pen-and-paper, closed-book examination.

AI can be used for the module by the students except during the tests and the final year examination.

Requirements, Exclusions and Recommendations

Not applicable to this module.


Module Requisites and Incompatibles
Not applicable to this module.
 

Assessment Strategy
Description Timing Component Scale Must Pass Component % of Final Grade In Module Component Repeat Offered
Exam (In-person): In-person test Week 6 Graded No
20
No
Exam (In-person): In-person test Week 11 Graded No
20
No
Exam (In-person): End of semester in-person examination End of trimester
Duration:
2 hr(s)
Graded No
60
No

Carry forward of passed components
Yes
 

Resit In Terminal Exam
Autumn Yes - 2 Hour
Please see Student Jargon Buster for more information about remediation types and timing. 

Feedback Strategy/Strategies

• Feedback individually to students, post-assessment

How will my Feedback be Delivered?

Not yet recorded.

Sarah Harris and David Harris
Digital Design and Computer Architecture, RISC-V Edition
Morgan Kaufmann
ISBN: 978-0128200643
1st edition
2021

David A. Patterson and John L. Hennessy
Computer Organization and Design RISC-V Edition: The Hardware Software Interface
Morgan Kaufmann
ISBN: 978-0128122754
1st edition
2017

John F. Wakerly
Digital Design: Principles and Practices
Pearson
ISBN: 978-0131863897
4th edition
2005

Charles Petzold
Code: The Hidden Language of Computer Hardware and Software
Microsoft Press
ISBN: 978-0137909100
2nd edition
2022

Name Role
Rashmi Erandika Ratnayake Tutor

Timetabling information is displayed only for guidance purposes, relates to the current Academic Year only and is subject to change.
Spring Practical Offering 1 Week(s) - 21, 22, 23, 24, 25, 26, 29, 30, 31, 32, 33 Wed 14:00 - 15:50