COMP30080 Computer Systems

Academic Year 2021/2022

This module is intended for students who wish to understand the relationship between computer software and hardware. The course is centred on the study of a real world microprocessor (MIPS32). Students will learn how to program in assembly language. The relationship between a processor's instruction set architecture and its performance is explained. Various processor designs are described including single-cycle, multi-cycle, pipelined and parallel. Design aspects of recent high-performance processor architectures are discussed.

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Curricular information is subject to change

Learning Outcomes:

On completion of this module students expected to be able to:
• Write, test and debug MIPS32 assembly language programs.
• Design and simulate simple logic circuits for simple processor.
• Explain the relationships between instruction set architecture, processor design and performance.
• Describe the most common processor organizations, understand how they operate and explain what their advantages and disadvantages are.
• Determine the performance of various design optimisations.
• Explain the operation of the computer memory systems including cache and main memory.
• Explain the operation of Java Virtual Machine and bytecode execution model.

Indicative Module Content:

Lecture 1: Introduction
Recaps on the basics of computer architecture and digital logic gates. Lectures 2-9: MIPS Assembly Language Programming
Students learn the syntax of MIPS assembly language and practice writing code fragments in class. Students are introduced to methods used to represent data in MIPS. Students learn the rules for converting MIPS assembly language to machine language and practice conversion examples in class. Students are given an overview of MIPS software development flow. Learning MIPS assembly language programming culminates with a case study examining a BubbleSort program.

Lectures 10-11: MIPS Processor Architecture & Organization
Students study the gate-level implementation of the MIP32 processor. The function and implementation of the main functional units (PC, Register File, ALU, Program RAM, Data RAM) are discussed in detail. Instruction execution is described in the context of the Von Neumann execution cycle.

Lecture 12: Computer Performance
Methods and metrics for evaluating and describing the performance of computer systems are explained. The advantages and disadvantages of various metrics are considered.

Lectures 13-20: Increasing Performance
Students learn about more advanced processor organizations intended to speed up processor execution, namely: multi-cycle execution, pipelining and parallelism. Techniques such as speculation, branch prediction and loop unrolling are explained, together with examples.

Lecture 21: Real-World Processors
The architectures and organizations of other current real-world processors are discussed, in particular, the Intel Architecture.

Lecture 22-24: Java Execution
Students learn how Java bytecode is written and is executed in a Java Virtual Machine. Contrasts will be drawn between the approach used for Java execution and that used in MIPS.

Practical 1-3: MIPS Assembly Language
Writing and verifying MIPS programs using the MARS Simulator. Starting with simple programs and moving to more complex problems involving processing of text and numbers.

Practical 4-5: Mini MIPS Processor
Development and verification of a cut-down MIPS processor implementation in the Logisim gate-level logic simulator. Design and execution of a machine language program on the processor.

Student Effort Hours: 
Student Effort Type Hours
Autonomous Student Learning

70

Lectures

24

Practical

22

Total

116

Approaches to Teaching and Learning:
Lecture-based content delivery.
Labs-based practical work.
Supplementary reading. 
Requirements, Exclusions and Recommendations
Learning Recommendations:

Students are recommended to have taken modules Comp10040 (Introduction to Computer Architecture) and Comp20020 (Digital Systems) or the equivalent of these modules.


Module Requisites and Incompatibles
Not applicable to this module.
 
Assessment Strategy  
Description Timing Open Book Exam Component Scale Must Pass Component % of Final Grade
Assignment: 5 assignments Varies over the Trimester n/a Alternative linear conversion grade scale 40% No

30

Examination: End of semester examination 2 hour End of Trimester Exam No Alternative linear conversion grade scale 40% No

70


Carry forward of passed components
No
 
Resit In Terminal Exam
Spring Yes - 2 Hour
Please see Student Jargon Buster for more information about remediation types and timing. 
Feedback Strategy/Strategies

• Feedback individually to students, post-assessment

How will my Feedback be Delivered?

Mark and written feedback will be provided online for submitted assignments.

David A. Patterson and John L. Hennessy, Computer Organization and Design MIPS Edition, Morgan Kaufmann.
David Harris and Sarah Harris, Digital Design and Computer Architecture, Morgan Kaufmann.
Name Role
Dr Arsalan Shahid Lecturer / Co-Lecturer
Dr Xiaoyu Du Tutor
Eric Gyamfi Tutor
Timetabling information is displayed only for guidance purposes, relates to the current Academic Year only and is subject to change.
 
Autumn
     
Lecture Offering 1 Week(s) - Autumn: All Weeks Thurs 11:00 - 11:50
Lecture Offering 1 Week(s) - Autumn: All Weeks Tues 12:00 - 12:50
Practical Offering 1 Week(s) - Autumn: All Weeks Wed 12:00 - 13:50
Practical Offering 2 Week(s) - Autumn: All Weeks Fri 14:00 - 15:50
Autumn