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COMP2007J

Academic Year 2024/2025

Principles of Computer Organiz (COMP2007J)

Subject:
Computer Science
College:
Science
School:
Computer Science
Level:
2 (Intermediate)
Credits:
5
Module Coordinator:
Dr Hadi Tabatabaee Malazi
Trimester:
Spring
Mode of Delivery:
Blended
Internship Module:
No
How will I be graded?
Letter grades
Campus of Delivery:
BDIC(UCD) Beijing

Curricular information is subject to change.

This module provides an introduction to the principles and their applications to the design of computer organisation. After examining the evolution of the digital computer, the module primarily focuses on the two fundamental components of a modern computer system: processor (datapath and control) and memory (principle of locality). Emphasis is placed on the performance benefits that can be gained from various organisational decisions, along with tradeoffs that are often required in designing a computer system. Another key topic throughout this module is the design of an instruction set (RISC-V) which defines the interface between hardware and software.

About this Module

Learning Outcomes:

On completing this module, students should be able to:
- describe the evolution of the modern computer system;
- assess the performance of a given computer system;
- understand the design of an instruction set (RISC-V) with the consideration of possible hardware organisations and high-level programming languages;
- understand the design of a processor (binary number representation, datapath, control, pipelining, parallelism, branch prediction, etc.);
- understand the design of a memory system (cache, memory, external memory, RAID, etc.)

Student Effort Hours:
Student Effort Type Hours
Lectures

30
Tutorial

14
Autonomous Student Learning

76
Total

120

Approaches to Teaching and Learning:
lectures, group work on the tutorial exercises

Requirements, Exclusions and Recommendations

Not applicable to this module.


Module Requisites and Incompatibles
Additional Information:
This module is delivered overseas and is not available to students based at the UCD Belfield or UCD Blackrock campuses.


 

Assessment Strategy
Description Timing Component Scale Must Pass Component % of Final Grade In Module Component Repeat Offered

Not yet recorded.

Carry forward of passed components
Yes
 

Resit In Terminal Exam
Summer Yes - 2 Hour
Please see Student Jargon Buster for more information about remediation types and timing. 

Feedback Strategy/Strategies

• Group/class feedback, post-assessment

How will my Feedback be Delivered?

Not yet recorded.

1. Hennessy, J. L., & Patterson, D. A. "Computer Organization and Design, RISC-V Edition: The Hardware Software Interface, 2nd Edition", 2021
2. Stallings, W. "Computer Organization and Architecture: Designing for Performance, 11th Edition", 2021

Name Role
Dr Seán Russell Lecturer / Co-Lecturer
Jiaying Guo Tutor
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