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Curricular information is subject to change
On completion of this module students are expected to:
• Understand the relationship between Boolean logic and circuit design.
• Design simple combinational circuits.
• Use binary number systems for calculation
• Use Karnaugh maps to simplify logic.
• Design simple sequential circuits.
• Interpret timing diagrams.
• Understand the behaviour of basic synchronous components such as D and JK-flip-flops.
• Design Mealy and Moore Finite State Machines.
• Understand how memory systems work.
• Understand for digital design issues.
Lectures 1-2:
Recap on the history of integrated circuits. Basic overview of how logic gates are constructed from transistors. Review of Boolean logic gates and truth tables.
Lectures 3-9:
Students learn how to design combinational logic circuits using Boolean logic gates. The design process is discussed together with design techniques, such as Karnaugh Maps. The relationship with Boolean algebra is explained with examples. Students also lean how to calculate the area and delay of circuits.
Lectures 10-17:
Student learn about the function, operation and design of memory circuits, including latches, flip- flops. ROMs and RAMs. They learn how to design Finite State Machines. Timing issues involving synchronous circuits are discussed.
Lectures 18-24:
Students learn how to design functional blocks, such as arithmetic circuits. Commonly used fixed and floating point number systems are described. Basic input and output devices are described. Student knowledge is integrated by means of system case studies.
Formative Assignment 1:
Design and implementation of digital circuits based on logic gates. Application of theory including truth tables, timing diagrams and Boolean algebra. Practice in circuit design, implementation and verification using the Logisim schematic-entry gate-level simulator.
Graded Assessment 1:
Design and implementation of combinational logic circuits using the Karnaugh map method.
Formative Assignment 2:
Design and implementation of circuits for performing binary arithmetic.
Design and implementation of Finite State Machines.
Graded Assessment 2:
Design and implementation of a mini computing machine.
Final End of Trimester Examination:
2 hours covering all aspects of the module.
Student Effort Type | Hours |
---|---|
Lectures | 24 |
Practical | 22 |
Autonomous Student Learning | 60 |
Total | 106 |
Not applicable to this module.
Description | Timing | Component Scale | % of Final Grade | ||
---|---|---|---|---|---|
Assignment: Assignment 2 (Graded) | Varies over the Trimester | n/a | Alternative linear conversion grade scale 40% | No | 10 |
Assignment: Assignment 4 (Graded) | Varies over the Trimester | n/a | Alternative linear conversion grade scale 40% | No | 10 |
Assignment: Assignment 3 (Graded) | Varies over the Trimester | n/a | Alternative linear conversion grade scale 40% | No | 10 |
Examination: End of trimester examination | 2 hour End of Trimester Exam | No | Alternative linear conversion grade scale 40% | No | 70 |
Resit In | Terminal Exam |
---|---|
Spring | Yes - 2 Hour |
• Feedback individually to students, post-assessment
Marks and written feedback are provided online for the assignment submissions.