BDIC3017J DSP Technology

Academic Year 2024/2025

Restriction: Beijing-based students only.

This is a practical DSP module that builds upon the theory learned earlier.
The purpose is to expose the student to real-world implementations of DSP algorithms including, but limited to, fixed point considerations, and resource constraint signal processing on an actual DSP IC.

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Curricular information is subject to change

Learning Outcomes:

Understand practical aspects to signal processing
Learn how to design hard-real-time signal processing algorithms
Learn how implement DSP algorithms on fixed point processors
Learn how implement DSP algorithms on resource constraint DSP ICs.

Student Effort Hours: 
Student Effort Type Hours
Lectures

36
Laboratories

16
Autonomous Student Learning

70
Total

122
Approaches to Teaching and Learning:
Lectures where material is explained coupled with Labs where the students see first had the principles.
 
Requirements, Exclusions and Recommendations

Not applicable to this module.


Module Requisites and Incompatibles
Required:
BDIC1047J - English for Uni Studies BDIC, BDIC1048J - English Gen Acad Purposes BDIC, BDIC2007J - English for Spec Acad Purposes, BDIC2015J - Acad Wrt & Comm Skills

Additional Information:
This module is delivered overseas and is not available to students based at the UCD Belfield or UCD Blackrock campuses


 
Assessment Strategy  
Description Timing Component Scale Must Pass Component % of Final Grade In Module Component Repeat Offered
Exam (In-person): 2 Hour Final Exam Week 15 Graded Yes

100

 Yes

Carry forward of passed components
Yes
 
Remediation Type Remediation Timing
In-Module Resit Prior to relevant Programme Exam Board
Please see Student Jargon Buster for more information about remediation types and timing. 
Feedback Strategy/Strategies

• Group/class feedback, post-assessment

How will my Feedback be Delivered?

Not yet recorded.

Name Role
Enchang Sun Tutor
Wenying Wu Tutor