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EEEN40600

Academic Year 2024/2025

Mixed-Signal Integrated Circuits (EEEN40600)

Subject:
Electronic & Electrical Eng
College:
Engineering & Architecture
School:
Electrical & Electronic Eng
Level:
4 (Masters)
Credits:
5
Module Coordinator:
Professor Robert Staszewski
Trimester:
Spring
Mode of Delivery:
On Campus
Internship Module:
No
How will I be graded?
Letter grades

Curricular information is subject to change.

Analysis and design of mixed-signal circuits, i.e., those combining both analogue and digital design techniques, concentrating on analogue-to-digital and digital-to-analogue converters (ADC & DAC). Topics include Nyquist-rate and oversampled sigma-delta data converters as well as effects of nonlinearities and noise on their system performance.
Note: This is continuation of EEEN 40570 - Analogue Integrated Circuits

About this Module

Learning Outcomes:

Gain skills in designing ADC and DAC circuits.Refine mixed-signal circuit design and behavioral modeling experience in Cadence CAD tools. Understand mixed-signal circuit tradeoffs on system performance.

Student Effort Hours:
Student Effort Type Hours
Specified Learning Activities

36

Autonomous Student Learning

24

Lectures

24

Computer Aided Lab

24

Total

108


Approaches to Teaching and Learning:
Traditional approach.

Requirements, Exclusions and Recommendations

Not applicable to this module.


Module Requisites and Incompatibles
Not applicable to this module.
 

Assessment Strategy
Description Timing Component Scale Must Pass Component % of Final Grade In Module Component Repeat Offered
Assignment(Including Essay): Homework assignments and reports on laboratory work. Timing may vary. Week 3, Week 4, Week 5, Week 6, Week 7, Week 8, Week 9, Week 10, Week 11 Standard conversion grade scale 40% No
40
No
Assignment(Including Essay): IEEE journal paper reading. Week 12 Standard conversion grade scale 40% No
20
No
Exam (In-person): Written exam at end of trimester End of trimester
Duration:
2 hr(s)
Standard conversion grade scale 40% No
40
No

Carry forward of passed components
Yes
 

Resit In Terminal Exam
Autumn Yes - 2 Hour
Please see Student Jargon Buster for more information about remediation types and timing. 

Feedback Strategy/Strategies

• Feedback individually to students, post-assessment

How will my Feedback be Delivered?

Not yet recorded.

Name Role
Dr Minh Hieu Nguyen Lecturer / Co-Lecturer
Dr Viet Nguyen Lecturer / Co-Lecturer
Dr Teerachot Siriburanon Lecturer / Co-Lecturer

Timetabling information is displayed only for guidance purposes, relates to the current Academic Year only and is subject to change.
Spring Lecture Offering 1 Week(s) - 20, 21, 22, 23, 24, 25, 26, 29, 30, 31, 32, 33 Thurs 12:00 - 12:50
Spring Laboratory Offering 1 Week(s) - 21, 22, 23, 24, 25, 26, 29, 30, 31, 32, 33 Thurs 13:00 - 14:50
Spring Lecture Offering 1 Week(s) - 20, 21, 22, 23, 24, 25, 26, 29, 30, 31, 32, 33 Tues 14:00 - 14:50